1. Field of the Invention
The present invention relates to the field of display technology, and in particular to a manufacturing method of a thin-film-transistor (TFT) substrate structure.
2. The Related Arts
A liquid crystal display (LCD) comprises an enclosure, a liquid crystal panel arranged in the enclosure, and a backlight module mounted in the enclosure. The liquid crystal panel is generally composed of a color filter (CF) substrate, a thin-film transistor (TFT) array substrate, and a liquid crystal layer filled between the two substrates. The CF substrate and the TFT substrate have inner surfaces facing each other and provided with transparent electrodes. The liquid crystal display is operated by providing an electric field to control the direction of liquid crystal molecules in order to change the state of polarization, and polarizers are involved to selectively to allow an optic path to pass or be blocked to thereby achieve the purpose of displaying.
The fringe field switching (FFS) technology is one of the techniques that have bee recently developed for improve image quality of LCDs and satisfies the requirements for both high transmittance and large view angle. FIG. 1 is a schematic view, in a sectioned form, showing a conventional TFT substrate of an FFS liquid crystal display panel, which comprises a base plate 100, a buffer layer 200 formed on the base plate 100, a gate terminal 300 formed on the buffer layer 200, a gate insulation layer 400 formed on the buffer layer 200 and covering the gate terminal 300, an island-like conductor layer 500 formed on the gate insulation layer 400, a source terminal 600 a the drain terminal 700 formed on the gate insulation layer 400 and respectively in contact with two side portions of the island-like conductor layer 500, a first passivation layer 800 formed on the gate insulation layer 400, the island-like semiconductor layer 500, the source terminal 600, and the drain terminal 700, a planarization layer 900 formed on the first passivation layer 800, a first pixel electrode 1000 formed on the planarization layer 900, a second passivation layer 1100 formed on the planarization layer 900 and the first pixel electrode 1000, and a second pixel electrode 1200 formed on the second passivation layer 1100. A via 1300 is formed in the second passivation layer 1100, the planarization layer 900, and the first passivation layer 800 to be located above and correspond to the drain terminal 700. The second pixel electrode 1200 is set in contact with the drain terminal 700 through the via 1300.
Referring to FIGS. 2-9, a known method for manufacturing the TFT substrate structure of the FFS liquid crystal display panel comprises the following steps:
Step 1: as shown in FIG. 2, providing a base plate 100 and depositing a buffer layer 200 on the base plate 100 and depositing a first metal layer on the buffer layer 200 and subjecting the first metal layer to patterning to form a gate terminal 300;
Step 2: as shown in FIG. 3, depositing a gate insulation layer 400 on the buffer layer 200 and the gate terminal 300 and depositing an oxide semiconductor layer on the gate insulation layer 400 and subjecting the oxide semiconductor layer to patterning to form an island-like semiconductor layer 500;
Step 3: as shown in FIG. 4, depositing a second metal layer on the gate insulation layer 400 and the island-like semiconductor layer 500 and subjecting the second metal layer to patterning to form a source terminal 600 and a drain terminal 700;
Step 4: as shown in FIG. 5, depositing a first passivation layer 800 on the gate insulation layer 400, the island-like semiconductor layer 500, the source terminal 600, and the drain terminal 700 and forming a first via 810 in the first passivation layer 800 to be located above and correspond to the drain terminal 700;
Step 5: as shown in FIG. 6, forming a planarization layer 900 on the first passivation layer 800 and forming a second via 901 in the planarization layer 900 to be located above and correspond to the first via 810;
Step 6: as shown in FIG. 7, depositing a first transparent conductive film on the planarization layer 900 and coating a photoresist layer 1101 on the first transparent conductive film,
wherein since the first and second vias 810, 910 are of a great depth, the photoresist layer 1101 may easily accumulate in the first and second vias 810, 910;
Step 7: as shown in FIG. 8, subjecting the photoresist layer 1101 to exposure and development,
wherein specifically, during the exposure and development, the portion of the photoresist layer 1101 that accumulates within the first and second vias 810, 910 may be susceptible to incomplete development, leading to residues of the photoresist layer 1101 remaining in the first and second vias 810, 910; and
Step 8: as shown in FIG. 9, with the photoresist layer 1101 as a shielding layer, subjecting a portion of the first transparent conductive film that is not shielded by the photoresist layer 1101 to etching so as to form a first pixel electrode 1000,
wherein since the portion of the first transparent conductive film located in the first and second vias 810, 910 may be covered by residues of the photoresist, it may not be completely removed in the etching process and the portion of first transparent conductive film may be left in the first and second vias 810, 910 and may thus affect a subsequent operation, leading to a negative influence on the quality of the TFT substrate.
Thus, in view of the problems and shortcomings of the known method, it is desired to provide an improved TFT substrate structure manufacturing method to overcome the problems of the known techniques.